1. Field of the Invention
The present invention relates to a semiconductor device comprising an active element such as a semiconductor chip, and a passive element such as a capacitor, these elements being mounted on a common substrate. The present invention also relates to a package structure of the semiconductor device, and a method for manufacturing the same.
2. Description of the Related Art
Recently, electronic apparatuses have been required to have carrying convenience and high performance with the popularization and advance of portable electronic apparatuses such as cellular phones and the like, and semiconductor devices used for such electronic apparatuses have been also required to be small, lightweight and thin, or multifunctional and inexpensive.
Therefore, there have been strong demand for module products or package products manufactured by a small and high-density packaging technology. Also, many multi-chip module (MCM) products, system in package (abbreviated to “SiP” hereinafter) products, and the like have been developed. In each of these products, a semiconductor chip and a passive element necessary for realizing a desired function are integrated in a package by using any one of various substrate materials.
However, a silicon substrate has conductivity and allows a leakage current and an induced current to flow therethrough, and thus the silicon substrate cannot be used as, for example, a SiP substrate for a RF (radio frequency) circuit of radio equipment or the like. Therefore, in a SiP for a RF circuit, a ceramic substrate such as a LTCC (Low-Temperature Co-Fired Ceramic) substrate or the like, an organic material substrate such as a FR-4 (flame retardant grade of U.S. National Electrical Manufacturers Association) glass epoxy substrate or the like is used as the substrate, and electric connection to a semiconductor chip is generally performed by flip chip bonding or wire bonding.
FIG. 13 is a schematic sectional view showing an example of a SiP for a RF circuit using LTCC substrates. Each of LTCC substrates 61 is formed by firing a clay-like sheet (generally referred to as a “green sheet”), which comprises alumina containing a filler, at a relatively low temperature of about 600° C. to 700° C. In order to form a SiP, a plurality of green sheets is laminated, pressed and then fired, as shown in FIG. 13.
The LTCC substrate 61 has the advantage of high thermal conductivity, high strength and no curvature, and also has the advantage that a passive element can be formed by printed wiring. Namely, each of an inductor 62 and a wiring portion 65 can be formed on the substrate by printing a printing paste comprising silver, tungsten, or the like on a green sheet. Also, a ceramic is a dielectric material, and thus each of capacitors 63 and 64 can be formed by forming electrodes opposing each other with a ceramic layer provided therebetween. Furthermore, a connecting portion 66 passing through the substrate can be formed by filling a printing paste in a hole (through hole) drilled in a green sheet.
However, the SiP using the LTCC substrates has the following problems 1 to 6:
1. Each of the layers cannot be sufficiently thinned (about 25 μm minimum, and usually about 50 μm). Thus, a SiP laminate cannot be easily thinned.
2. Connection to semiconductor chips 67 and 68 can be performed only by flip chip bonding or wire bonding. The flip chip bonding requires a space for filling an underfill material 69, and the space projects from the chip size in a planar direction to produce a region where another element cannot be disposed. The wire bonding requires a space for providing a wire. Any one of the bonding methods is difficult of compact packaging.
3. The semiconductor chips cannot be buried in a ceramic layer because firing is performed. Therefore, the semiconductor chips must be fixed to the top of the substrate as described above, and thus a protective material is required to increase the size.
4. A pattern can be formed only by printing.
5. The laminated ceramic layers must have the same degree of thermal expansion coefficient, and thus the same material must be used for the ceramic layers.
6. As a result, the dielectric constant of each layer is limited to cause difficulty in changing the dielectric constant with the layers, thereby limiting the capacitance.
7. The cost is increased.
On the other hand, 14A is a schematic sectional view of an example of a RF SiP using a glass epoxy substrate such as the FR-4 substrate or the like. Although a glass epoxy substrate 71 can easily be processed by drilling or laser boring, the substrate 71 has a thickness of as large as about 150 μm and a low dielectric constant, thereby causing the problem of failing to form a capacitor by using the substrate itself (but, an inductor 72 can be incorporated). Therefore, like in the LTCC substrate, a user connects a semiconductor chip 77 to the substrate by flip chip bonding or wire bonding, and connects a passive element 78 such as a capacitor or the like to the substrate by solder bonding (wireless bonding), thereby causing difficulty in compact packaging.
As shown in FIG. 14B, there has been a study of burying of en electronic component in a glass epoxy substrate. However, the electronic component has a large thickness, and thus the thickness of a layer in which the electronic component such as a semiconductor chip or the like is buried reaches 400 μm to 600 μm, thereby failing to decrease the thickness of the whole SiP and making it difficult to satisfy the requirement for thinning of a mobile product or the like.
Therefore, a method of thinning the buried semiconductor chip to decrease the whole thickness has been studied. However, a conventional method for thinning a semiconductor chip comprises grinding a support substrate, and thus requires new apparatuses other than an apparatus for bonding a back grind protecting tape, such as an apparatus for bonding to the support substrate, and an apparatus for separating the tape. Also, the number of the materials used is increased to increase the material cost and the SiP cost.
A method for precisely fixing a semiconductor chip in a face up state has an accuracy limit of 15 μm in a case of flip chip bonding, and an accuracy limit of 35 μm in a case of wire bonding (refer to Japanese Unexamined Patent Application Publication Nos. 2-150041, 5-343449, and 11-26481). For a laser light emitting element, a die bonder for realizing an accuracy of about 5 μm has been developed. However, the die bonder cannot be used for a large-diameter wafer or substrate because the tact time is long, and the accuracy is adversely affected by heat.
A possible method comprises mounting a semiconductor chip in a face up state on a silicon substrate having high reliability, burying a passive element in an insulating layer to mount it on the silicon substrate, and then forming wiring between the elements. However, this method has difficulty in thinning and miniaturization in any one of the planar direction and the height direction because there is now no bonding method other than flip chip bonding and wire bonding.
On the other hand, for the semiconductor chips, it has been proposed that the semiconductor chips are separately produced and integrated by an interlayer insulating film or the like, for realizing compact packaging and good circuit characteristics (refer to Japanese Unexamined Patent Application Publication Nos. 2001-298149 (pages 4 to 6 and FIGS. 1 and 13), and 2001-189424 (pages 6 to 10, and FIGS. 2, 4, 6 and 8)).
For example, Japanese Unexamined Patent Application Publication No. 2001-298149 discloses a semiconductor device comprising a semiconductor substrate, a circuit having a predetermined function and at least one recess which are formed on the semiconductor substrate, a semiconductor chip previously formed and buried in the recess, and an insulating layer for filling in a step between the semiconductor substrate and the semiconductor chip. This document also discloses a method according to an embodiment comprising forming contact holes in the insulating layer at necessary positions, and then bonding integrated circuits on the semiconductor chips with metal wiring of aluminum or the like. Japanese Unexamined Patent Application Publication No. 2001-189424 discloses various arrangement methods for laminating and mounting a plurality of semiconductor chips in a face up state.
However, in any one of these methods, no consideration is given to the manufacture and mounting of a passive element. In the invention of Japanese Unexamined Patent Application Publication No. 2001-298149, all semiconductor chips are mounted on one substrate, and there is thus the problem of increasing the substrate area as the number of the semiconductor ships mounted on the substrate increases. On the other hand, the invention of Japanese Unexamined Patent Application Publication No. 2001-189424 is aimed only at mounting about 2 to 3 semiconductor chips with a high density, and thus another substrate is required for mounting stacked semiconductor chips.